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FEATURES
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LT3507 Triple Monolithic Step-Down Regulator with LDO DESCRIPTION
The LT(R)3507 is a triple, current mode, DC/DC converter with internal power switches and a low dropout regulator. The switching converters are step-down converters capable of generating one 2.4A output and two 1.5A outputs. All three converters are synchronized to a single oscillator. The 2.4A output runs with opposite phase to the other two converters, reducing input ripple current. Each regulator has independent shutdown and soft-start circuits, and generates a power good signal when its output is in regulation, easing power supply sequencing and interfacing with microcontrollers and DSPs. The switching frequency is set with a single resistor yielding a range of 250kHz to 2.5MHz. The high switching frequency allows the use of small inductors and capacitors resulting in a very small triple output supply. The constant switching frequency, combined with low impedance ceramic capacitors, results in low, predictable output ripple. With its wide input voltage range of 4V to 36V, the LT3507 regulates a broad array of power sources including 5V logic rails, unregulated wall transformers, lead acid batteries and distributed power supplies.
Wide Input Range: 4V to 36V One 2.4A and Two 1.5A Output Switching Regulators with Internal Power Switches Low Dropout Linear Regulator with External Transistor Antiphase Switching Reduces Ripple Independent Run, Tracking/Soft-Start, and Power Good Indicators Ease Supply Sequencing Uses Small Inductors and Ceramic Capacitors Adjustable, 250kHz to 2.5MHz Switching Frequency, Synchronizable Over the Full Range User Programmable Overvoltage and Undervoltage Lockouts Thermally Enhanced, 38-Lead 5mm x 7mm QFN Package DSL and Cable Modems Distributed Power Regulation DSP Power Automotive
APPLICATIONS
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L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
5V, 3.3V, 2.5V and 1.8V Step-Down Regulator
VIN 6V TO 36V 22F VIN1 BOOST1 VOUT1 1.8V 2.4A 4.7H 0.22F SW1 18.7k 100F 15k 18.7k 680pF VC1 0.22F BOOST3 SW3 53.6k 22F 10.2k 24.3k 680pF VC3 RT/SYNC DRIVE 24.3k FB4 GND 11.5k 2.2F 107k VOUT4 2.5V 0.2A FB3 BIAS LT3507 FB2 1000pF VC2 11.5k 16.2k 35.7k 10H FB1 SW2 VOUT2 3.3V 1.3A 22F 0.22F VIN2 VIN3 BOOST2
Start-Up Waveforms--Coincident Tracking
VOUT3 VOUT2 VOUT4 VOUT1
1V/DIV
VOUT2 VOUT3 5V 1.5A 15H
1ms/DIV
3507 TA01b
fSW = 450kHz
3507 TA01a
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LT3507 ABSOLUTE MAXIMUM RATINGS
(Note 1)
PIN CONFIGURATION
BOOST3 31 VIN2 30 VIN2 29 SW2 28 SW2 27 BOOST2 39 26 TRK/SS4 25 FB4 24 DRIVE 23 VC2 22 FB2 21 TRK/SS2 20 FB3 13 14 15 16 17 18 19 RT/SYNC BIAS TRK/SS3 RUN1 RUN2 RUN3 VC3 TOP VIEW SW1 SW1 SW3 SW3 VIN3 VIN3
VIN Pins...................................................... -0.3V to 36V BOOST Pins ..............................................................55V BOOST Above SW .....................................................25V PGOOD Pins..............................................................36V BIAS Pin....................................................................16V TRK/SS, VC, FB, RT/SYNC Pins ...................................6V RUN, OVLO, UVLO Pins ........................................... VIN1 DRIVE Pin ...................................................................5V Operating Junction Temperature Range (Notes 2, 5) LT3507E, LT3507I .............................. -40C to 125C LT3507H ............................................ -40C to 150C Storage Temperature Range................... -65C to 150C
38 37 36 35 34 33 32 BOOST1 1 VIN1 2 VIN1 3 VINSW 4 OVLO 5 UVLO 6 VC1 7 TRK/SS1 8 FB1 9 PGOOD1 10 PGOOD2 11 PGOOD3 12
UHF PACKAGE 38-LEAD (5mm x 7mm) PLASTIC QFN JA = 34C/W EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH LT3507EUHF#PBF LT3507IUHF#PBF LT3507HUHF#PBF TAPE AND REEL LT3507EUHF#TRPBF LT3507IUHF#TRPBF LT3507HUHF#TRPBF PART MARKING* 3507 3507 3507 PACKAGE DESCRIPTION 38-Lead (5mm x 7mm) Plastic QFN 38-Lead (5mm x 7mm) Plastic QFN 38-Lead (5mm x 7mm) Plastic QFN TEMPERATURE RANGE -40C to 125C -40C to 125C -40C to 150C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN1, VIN2, VIN3 = 12V, VBOOST1, VBOOST2, VBOOST3 = 17V, unless otherwise noted. (Note 2)
PARAMETER Minimum Operating Voltage Input Quiescent Current Bias Quiescent Current Shutdown Current Reference Voltage Line Regulation CONDITIONS Internal UVLO on VIN1 Not Switching, VBIAS = 3.3V Not Switching, VBIAS = 3.3V VRUN1,2,3 = 0V 5V < VIN1 < 36V 0.01
l
ELECTRICAL CHARACTERISTICS
MIN
TYP 3.8 2 5
MAX 4 3.5 7.5 1
UNITS V mA mA A %/V
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LT3507 ELECTRICAL CHARACTERISTICS
PARAMETER VC Source Current VC Sink Current VC Clamp Voltage Switching Frequency Switching Phase Foldback Frequency Frequency Shift Threshold on FB RUN Threshold PGOOD Output Voltage Low PGOOD Pin Leakage PGOOD Threshold Offset Feedback Pin Voltage Feedback Pin Bias Current Error Amplifier Transconductance Error Amplifier Voltage Gain VC Switching Threshold Switch Leakage Current Minimum Boost Voltage Above Switch (Note 4) Converter 1 VC1 to Switch Current Gain Switch 1 Current Limit (Note 3) Switch 1 VCESAT BOOST1 Operating Current Converter 2 VC2 to Switch Current Gain Switch 2 Current Limit (Note 3) Switch 2 VCESAT BOOST2 Operating Current Converter 3 VC3 to Switch Current Gain Switch 3 Current Limit (Note 3) Switch 3 VCESAT BOOST3 Operating Current LDO Regulator Feedback Pin Voltage Feedback Pin Bias Current Error Amplifier Voltage Gain Line Regulation VIN from 5V to 36V
l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN1, VIN2, VIN3 = 12V, VBOOST1, VBOOST2, VBOOST3 = 17V, unless otherwise noted. (Note 2)
CONDITIONS VC = 0.6V VC = 0.6V RT = 40.2k SW1 to SW2,3, RT = 40.2k VFB = 0V, RT = 40.2k
l
MIN
TYP 100 100 1.7
MAX
UNITS A A V
0.9 180 120 0.4 1
1.1
MHz Deg kHz V
1.5 0.4 400 105 812 -500
V V nA mV mV nA S V/V V
IPGOOD = 200A VPGOOD = 2V VFB Rising
l l
0.2 10 58 788 80 800 -50 330 500 0.9 0.01 1.8 5
10 2.5
A V A/V
Duty Cycle = 15% ISW1 = 2A ISW1 = 2A
l
3
4.3 400 40 3.6
6 600 60
A mV mA A/V
Duty Cycle = 15% ISW2 = 1.5A ISW2 = 1.5A
l
2
2.9 350 40 3.6
4 500 60
A mV mA A/V
Duty Cycle = 15% ISW3 = 1.5A ISW3 = 1.5A
l
2
2.9 350 40
4 500 60 812 -500
A mV mA mV nA V/V %/V
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800 -150 1100 0.05
3
LT3507 ELECTRICAL CHARACTERISTICS
PARAMETER Load Regulation DRIVE Output Current Limit Dropout Voltage, VIN1 to DRIVE Dropout Voltage, BIAS to DRIVE Over/Undervoltage Lockout Undervoltage Lockout Threshold Overvoltage Lockout Threhold Undervoltage Lockout Hysteresis Current Overvoltage Lockout Hysteresis Current Input Bias Current (OVLO and UVLO) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3507E is guaranteed to meet performance specifications from 0C to 125C junction temperature. Specifications over the -40C to 125C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3507I is guaranteed to meet performance specifications from -40C to 125C junction temperature. The LT3507H is guaranteed over the full -40C to 150C operating junction temperature range. High junction temperatures degrade operating lifetimes. Operating lifetime is derated at junction temperatures greater than 125C. V(UVLO) < 1.2V V(OVLO) > 1.2V 1.15 1.15 7 -7 1.20 1.20 10 -10 -100 1.25 1.25 13 -13 -200 V V A A nA IDRIVE = 10mA IDRIVE = 10mA
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN1, VIN2, VIN3 = 12V, VBOOST1, VBOOST2, VBOOST3 = 17V, unless otherwise noted (Note 2)
CONDITIONS IDRIVE from 0.1mA to 10mA
l
MIN 10
TYP 0.005 15 1.7 0.5
MAX 22.5 2.0 0.8
UNITS %/mA mA V V
Note 3: Current limit is guaranteed by design and/or correlation to static test. Slope compensation reduces current limit at higher duty cycles. Note 4: This is the minimum voltage across the boost capacitor needed to guarantee full saturation of the internal power switch. Note 5: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed the maximum operating range when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability.
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LT3507 TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Current, Channel 1, VOUT = 1.8V
90 TA = 25C fSW = 450kHz VIN = 6V EFFICIENCY (%) VIN = 12V 70 VIN = 36V 60 100 90 80 70 60 50 40 0 0.5 1 1.5 IOUT (A) 2 2.5
3507 G01
Efficiency vs Load Current, Channels 2 and 3, VOUT = 3.3V
TA = 25C fSW = 450kHz VIN = 6V VIN = 12V VIN = 36V VSW (V) 0.6 0.5 0.4 0.3 0.2 0.1 0
Switch VCESAT vs Switch Current, Channels 1, 2 and 3
TA = 25C
80 EFFICIENCY (%)
CHANNELS 2 & 3 CHANNEL 1
50
40
0
0.3
0.9 0.6 IOUT (A)
1.2
1.5
3507 G02
0
0.5
1
1.5 ISW (A)
2
2.5
3
3507 G03
BOOST Pin Current vs Switch Current, Channels 1, 2 and 3
100 90 80 70 IBOOST (mA) VFB (mV) 60 50 40 30 20 10 0 0 0.5 1 1.5 ISW (A) 2 2.5 3
3507 G04
VFB vs Temperature
805 804 803 2.5
Frequency vs RT
TA = 25C
TA = 25C
CHANNELS 2 & 3
801 800 799 798 797 796 795 -50 -30 -10 30 50 70 90 110 130 150 TEMPERATURE (C)
3507 G05
CHANNEL 1
FREQUENCY (MHz) 0.25 10 RT (k)
3507 G06
802
100
Frequency vs Temperature
0.5 1200 1000 FRERQUENCY (kHz) 800
Frequency vs VFB (Foldback)
RT = 40.2k TA = 25C 1.30
ITRK/SS vs Temperature
FREQUENCY DEVIATION (%)
0.0
1.28
-0.5
ITRK/SS (A) 0 0.2 0.4 0.6 VFB (V) 0.8 1
3507 G08
1.26
600 400 200 0
-1.0
1.24
-1.5
1.22
-2.0 -50 -30 -10 30 50 70 90 110 130 150 TEMPERATURE (C)
3507 G07
1.20 -50 -30 -10 30 50 70 90 110 130 150 TEMPERATURE (C)
3507 G09
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LT3507 TYPICAL PERFORMANCE CHARACTERISTICS
RUN Threshold vs Temperature
1.2 1.0 RUN THRESHOLD (V) 0.8 0.6 0.4 0.2 0.0 -50 -30 -10 30 50 70 90 110 130 150 TEMPERATURE (C)
3507 G10
VIN1-VINSW Voltage Drop vs IVINSW
0.40 0.35 0.30 VIN-VINSW (V) 0.25 ILIM (A) 0.20 0.15 0.10 0.05 0.00 0 0.2 0.4 0.6 IVINSW (mA) 0.8 1.0
3507 G12
Current Limit vs Duty Cycle
4.5 4.0 CHANNEL 1 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 20 40 60 DUTY CYCLE (%) 80 100
3507 G13
TA = 25C
TA = 25C
CHANNELS 2 & 3
Minimum On-Time vs ISW
250 200
Minimum Off-Time vs ISW
200 MINIMUM OFF-TIME (ns) MINIMUM ON-TIME (ns) 150
-40C 25C 150C
150 150C 100 -40C 25C
100
50
50
0
0
1 ISW (A)
2
3
3507 G14
0
0
0.5
1
1.5 ISW (A)
2
2.5
3
3507 G15
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LT3507 PIN FUNCTIONS
BOOST1, BOOST2, BOOST3 (Pins 1, 27, 32): The BOOST pins are used to provide drive voltages, higher than the input voltage, to the internal bipolar NPN power switches. These pins must be tied through a diode from VOUT, VIN or another supply greater than 2.5V. VIN1 (Pins 2, 3): The VIN1 pins supply power to the internal switch of the 2.4A regulator and to the LT3507's internal reference and start-up circuitry. These pins must be locally bypassed (Note 6). VINSW (Pin 4): The VINSW pin is a switched VIN1 for the user programmable undervoltage and overvoltage detection. It is connected to VIN1 when any of the RUN pins are pulled high, and high impedance when all RUN pins are low or open. OVLO (Pin 5): The LT3507 goes into overvoltage shutdown when this pin goes above 1.2V. If unused, the OVLO pin should be tied to GND. UVLO (Pin 6): The LT3507 goes into undervoltage shutdown when this pin drops below 1.2V. If unused, the UVLO pin should be tied to VINSW. VC1, VC2, VC3 (Pins 7, 23, 19): The VC pins are the outputs of the internal error amps. The voltages on these pins control the peak switch currents. These pins are normally used to compensate the control loops. Each switching regulator can be shut down by pulling its respective VC pin to ground with an NMOS or NPN transistor. TRK/SS1, TRK/SS2, TRK/SS3, TRK/SS4 (Pins 8, 21, 18, 26): The TRK/SS pins allow a regulator to track the output of another regulator. When the TRK/SS pin is below 0.8V, the FB pin regulates to the TRK/SS voltage. This pin can also be used as a soft-start by connecting a capacitor from TRK/SS to ground. The TRK/SS pins should be left open if neither feature is used. FB1, FB2, FB3 (Pins 9, 22, 20): The FB pins are the negative inputs of the error amplifiers. The LT3507 regulates each feedback pin to the lesser of 0.8V or the TRK/SS pin voltage. Connect the feedback resistor divider taps to these pins. PGOOD1, PGOOD2, PGOOD3 (Pins 10, 11, 12): The PGOOD pins are the open-collector outputs of an internal comparator. PGOOD remains low until the FB pin is within 10% of the final regulation voltage. As well as indicating output regulation, the PGOOD pins can sequence the switching regulators. These pins must be left unconnected if unused. The PGOOD outputs are valid when VIN is greater than 3.5V and any of the RUN pins are high. They are not valid when all RUN pins are low. RT/SYNC (Pin 13): The RT/SYNC pin requires a resistor to ground or a clock signal to set the operating frequency of the LT3507. RUN1, RUN2, RUN3 (Pins 14, 15, 16): The RUN pins are used to shut down the individual switching regulators. When all three RUN pins are low, the LT3507 shuts down and draws less than 1A from VIN1. BIAS (Pin 17): The BIAS pin supplies the current to the LT3507's internal regulator. This pin should be tied to the lowest available voltage source above 3V (either VIN, VOUT or any other available supply). The LDO pass transistor's base current is supplied from the BIAS pin if it is at least 0.8V above the LDO DRIVE output. DRIVE (Pin 24): The DRIVE pin provides the base drive for an external NPN transistor used for the LDO regulator. FB4 (Pin 25): The FB4 pin is the negative input to the LDO error amplifier. It is regulated to 0.8V through the LDO feedback resistor divider. VIN2 (Pins 30, 31)/VIN3 (Pins 35, 36 ): The VIN2 and VIN3 pins supply power to the internal switches of the 1.5A converters. These pins must be locally bypassed (Note 6). SW1 (Pins 37, 38)/SW2 (Pins 28, 29)/SW3 (Pins 33, 34): The SW pins are the outputs of the internal power switches. Connect these pins to the inductors and switching diodes. Exposed Pad (Pin 39): Ground. The underside Exposed Pad metal of the package provides both electrical contact to ground and good thermal contact to the printed circuit board. The Exposed Pad must be soldered to a grounded pad on the circuit board for proper operation.
Note 6: VINX pins that are connected together may share a bypass capacitor.
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LT3507 BLOCK DIAGRAM
VIN1 VINSW
+
BIAS RUN1 RUN2 RUN3 RT/SYNC CLK1 CLK2 CLK3
OVLO
-
INT REG AND REF MASTER OSC 1.2V
+ -
UVLO VIN4 DRIVE VOUT4 SHDN THERMAL SHUTDOWN
+ + -
TRK/SS4 0.8V FB4
CHANNEL SHUTDOWN
UNDERVOLTAGE DETECTION
VIN
VINX CIN
+ + +
0.9V SLOPE
+ -
C1 R SQ
-
BOOST
D2
C3 L1 VOUTX D1 C1
CLK
SLAVE OSC SW
+ -
VC CF RC CC 0.4V FB 1.25A 0.8V
- ERROR - AMP + + + -
R1 R2
PGOOD
1.7V
GND ONE OF THREE STEP-DOWN REGULATORS
Figure 1. LT3507 Block Diagram with Typical External Components
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+
-
ILIMIT CLAMP
80mV TRK/SS
3507 F01
LT3507 OPERATION
The LT3507 contains three independent, constant frequency, current mode, switching regulators with internal power switches plus a low dropout linear regulator. The three regulators share common circuitry including input source, voltage reference and oscillator, but are otherwise independent. Operation can be best understood by referring to the Block Diagram (Figure 1). If the RUN pins are tied to ground, the LT3507 is shut down and draws <1A from the input source tied to VIN1. If any of the RUN pins are driven above 1V, the internal bias circuits turn on, including the internal regulator, reference, and master oscillator. Each switching regulator will only begin to operate when its corresponding RUN pin reaches >1.25V. The master oscillator generates three clock signals, with the signal for Channel 1 out of phase by 180. The three switchers are current mode regulators. Instead of directly modulating the duty cycle of the power switch, the feedback loop controls the peak current in the switch during each cycle. Compared to voltage mode control, current mode control improves loop dynamics and provides cycle-by-cycle current limit. The Block Diagram shows only one of the three step-down switching regulators. A pulse from the slave oscillator sets the RS flip-flop and turns on the internal NPN bipolar power switch. Current in the switch and the external inductor begins to increase. When this current exceeds a level determined by the voltage at VC, current comparator C1 resets the flip-flop, turning off the switch. The current in the inductor flows through the external Schottky diode and begins to decrease. The cycle begins again at the next pulse from the oscillator. In this way, the voltage on the VC pin controls the current through the inductor to the output. The internal error amplifier regulates the output voltage by continually adjusting the VC pin voltage. The threshold for switching on the VC pin is >1V and an active clamp of 1.8V limits the output current. Each switcher contains an extra, independent oscillator to perform frequency foldback during overload conditions. This slave oscillator is normally synchronized to the master oscillator. A comparator senses when VFB is less than 50% of its regulated value and switches the regulator from the master oscillator to a slower slave oscillator. VFB is less than 50% of its regulated value during start-up, short-circuit and overload conditions. Frequency foldback helps limit switch current under these conditions. The TRK/SS pins override the 0.8V reference for the FB pins when the TRK/SS pins are below 0.8V. This allows either coincident or ratiometric supply tracking on start-up as well as a soft-start capability. The switch drivers operate either from VIN or from the BOOST pin. An external capacitor and diode are used to generate a voltage at the BOOST pin that is higher than the input supply. This allows the driver to saturate the internal bipolar NPN power switch for efficient operation. The BIAS pin allows the internal circuitry to draw its current from a lower voltage supply than the input, also reducing power dissipation and increasing efficiency. If the voltage on the BIAS pin falls below 3V, then its quiescent current will flow from VIN. A power good comparator trips when the FB pin is at 90% of its regulated value. The PGOOD output is an open-collector transistor that is off when the output is in regulation, allowing an external resistor to pull the PGOOD pin high. Power good is valid when the LT3507 is enabled and VIN > 3.5V. The LDO regulator uses an external NPN pass transistor to form a linear regulator. The loop is internally compensated to be stable with a load capacitance of 2.2F or greater. The LDO is disabled when all three of the RUN pins are low. The overvoltage and undervoltage detection shuts down the LT3507 if the input voltage goes above or below resistor programmable thresholds. The hysteresis of these detectors is also resistor programmable.
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LT3507 APPLICATIONS INFORMATION
STEP-DOWN CONSIDERATIONS FB Resistor Network The output voltage is programmed with a resistor divider (refer to the Block Diagram) between the output and the FB pin. Choose the resistors according to: R1= R2 VOUT -1 800mV DCMAX = 1 1+ 1 B
where B is the output current capacity divided by the typical boost current from the BOOST pin current vs switch current in the Typical Performance Characteristics section. The maximum operating voltage without pulse skipping is determined by the minimum duty cycle DCMIN: VIN(PS) = VOUT + VF - VF + VSW DCMIN
The parallel combination of R1 and R2 should be 10k or less to avoid bias current errors. Input Voltage Range The minimum operating voltage is determined either by the LT3507's internal undervoltage lockout (4V on VIN1, 3V on VIN2 and VIN3) or by its maximum duty cycle. The duty cycle is the fraction of time that the internal switch is on and is determined by the input and output voltages: DC = VOUT + VF VIN - VSW + VF
with DCMIN = tON(MIN) * fSW. Thus both the maximum and minimum input voltages are a function of the switching frequency and output voltages. Therefore the maximum switching frequency must be set to a value that accommodates all the input and output voltage parameters and must meet both of the following criteria for each channel: fMAX1 = VOUT + VF 1 * VIN(PS) - VSW + VF tON(MIN) VOUT + VF 1 * VIN(MIN) - VSW + VF tOFF(MIN)
where VF is the forward voltage drop of the catch diode (~0.4V) and VSW is the voltage drop of the internal switch (~0.3V at maximum load). This leads to a minimum input voltage of: VIN(MIN) = VOUT + VF - VF + VSW DCMAX
fMAX2 = 1-
The duty cycle is the fraction of time that the internal switch is on during a clock cycle. The maximum duty cycle is generally given by DCMAX = 1- tOFF(MIN)* fSW. However, unlike most fixed frequency regulators, the LT3507 will not switch off at the end of each clock cycle if there is sufficient voltage across the boost capacitor (C3 in Figure 1) to fully saturate the output switch. Forced switch off for a minimum time will only occur at the end of a clock cycle when the boost capacitor needs to be recharged. This operation has the same effect as lowering the clock frequency for a fixed off time, resulting in a higher duty cycle and lower minimum input voltage. The resultant duty cycle depends on the charging times of the boost capacitor and can be approximated by the following equation:
The values of tON(MIN) and tOFF(MIN) are functions of ISW and temperature (see chart in the Typical Performance Characteristics section). Worst-case values for switch currents greater than 0.5A are tON(MIN) = 130ns (for TJ > 125C tON(MIN) = 155ns) and tOFF(MIN) = 170ns. fMAX1 is the frequency at which the minimum duty cycle is exceeded. The regulator will skip ON pulses in order to reduce the overall duty cycle at frequencies above fMAX1. It will continue to regulate but with increased inductor current and greatly increased output ripple. The increased peak inductor current in pulse skipping will also stress the switch transistor at high voltages and high switching frequency. If the LT3507 is allowed to pulse skip and the input voltage is greater than 20V, then the switching frequency must be kept below 1.1MHz to prevent damage to the LT3507.
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LT3507 APPLICATIONS INFORMATION
fMAX2 is the frequency at which the maximum duty cycle is exceeded. If there is sufficient charge on the BOOST capacitor, the regulator will skip OFF periods to increase the overall duty cycle at frequencies about fMAX2. It will continue to regulate but with increased inductor current and greatly increased output ripple. Note that the restriction on the operating input voltage refers to steady-state limits to keep the output in regulation; the circuit will tolerate input voltage transients up to the absolute maximum rating. Switching Frequency Once the upper and lower bounds for the switching frequency are found from the duty cycle requirements, the frequency may be set within those bounds. Lower frequencies result in lower switching losses, but require larger inductors and capacitors. The user must decide the best trade-off. The switching frequency is set by a resistor connected from the RT/SYNC pin to ground, or by forcing a clock signal into RT/SYNC. The LT3507 applies a voltage of ~1.25V across this resistor and uses the current to set the oscillator speed. The switching frequency is given by the following formula: fSW = 55 R T + 12
VCC CLOCK SYNC CLK 1k 470pF LT3507 RT/SYNC SW1 BAS70 RT
3507 F02
VOUT1
Figure 2. Clock Powered from LT3507 Output
Inductor Selection and Maximum Output Current The current in the inductor is a triangle wave with an average value equal to the load current. The peak switch current is equal to the output current plus half the peak-to-peak inductor ripple current. The LT3507 limits its switch current in order to protect itself and the system from overload faults. Therefore, the maximum output current that the LT3507 will deliver depends on the switch current limit, the inductor value and the input and output voltages. When the switch is off, the potential across the inductor is the output voltage plus the catch diode drop. This gives the peak-to-peak ripple current in the inductor: IL = (1- DC) VOUT + VF L*f
where f is the switching frequency of the LT3507 and L is the value of the inductor. The peak inductor and switch current is: ISWPK =ILPK =IOUT + IL 2
where fSW is in MHz and RT is in k. The frequency sync signal will support VH logic levels from 1.8V to 5V CMOS or TTL. The duty cycle is not important, but it needs a minimum on time of 100ns and a minimum off time of 100ns. If the sync circuit is to be powered from one of the LT3507 outputs there may be start-up problems if the driving gate is high impedance without a supply or pulls high or low at some intermediate supply voltage. The circuit shown in Figure 2 prevents these problems by isolating the clock sync circuit until the clock is operating. The Schottky diode should be a low leakage type such as the BAS70 from On Semi or CMOD6263 from Central Semi. RT should be set to provide a frequency within 25% of the final sync frequency.
To maintain output regulation, this peak current must be less than the LT3507's switch current limit, ILIM. For SW1, ILIM is at least 3A at low duty cycles and decreases linearly to 2.4A at DC = 0.8. For SW2 and SW3, ILIM is at least 2A for at low duty cycles and decreases linearly to 1.6A at DC = 0.8. The minimum inductance can now be calculated as: LMIN = 1- DCMIN VOUT + VF * 2*f ILIM - IOUT
However, it's generally better to use an inductor larger than the minimum value. The minimum inductor has large ripple currents which increase core losses and require large output capacitors to keep output voltage ripple low.
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LT3507 APPLICATIONS INFORMATION
Select an inductor greater than LMIN that keeps the ripple current below 30% of ILIM. The inductor's RMS current rating must be greater than the maximum load current and its saturation current should be greater than ILPK. For highest efficiency, the series resistance (DCR) should be less than 0.1. Table 1 lists several vendors and types that are suitable.
Table 1. Inductors
PART NUMBER Sumida CDC5D23-2R2 CDRH5D28-2R6 CDRH6D26-5R6 CDH113-100 Coilcraft DO1606T-152 LPS6225-222ML DO1608C-332 MSS6132-472ML DO1813P-682HC Cooper SD414-2R2 DRA73-6R8-R UP1B-100 Toko (D62F)847FY-2R4M (D73LF)817FY-2R2M 2.4 2.2 2.5 2.7 0.037 0.03 2.7 3.0 2.2 6.8 10 2.73 2.96 1.90 0.061 0.041 0.111 1.35 3.55 5.0 1.5 2.2 3.3 4.7 6.8 2.10 4.00 2.00 2.60 2.20 0.060 0.045 0.080 0.056 0.080 2.0 2.4 2.9 3.2 5.0 2.2 2.6 5.6 10 2.16 2.60 2.00 2.00 0.030 0.013 0.027 0.047 2.5 3.0 2.8 3.7 VALUE (H) ISAT (A) DCR () HEIGHT (mm)
Output Capacitor Selection The output capacitor filters the inductor current to generate an output with low voltage ripple. It also stores energy in order to satisfy transient loads and stabilize the LT3507's control loop. Because the LT3507 operates at a high frequency, minimal output capacitance is necessary. In addition, the control loop operates well with or without the presence of output capacitor series resistance (ESR). Ceramic capacitors, which achieve very low output ripple and small circuit size, are therefore an option. You can estimate output ripple with the following equations: VRIPPLE = IL for ceramic capacitors 8 * f * COUT
and VRIPPLE = IL * ESR for electrolytic capacitors (tantalum and aluminum) where IL is the peak-to-peak ripple current in the inductor. The RMS content of this ripple is very low so the RMS current rating of the output capacitor is usually not of concern. It can be estimated with the formula: IC(RMS) = IL 12
This analysis is valid for continuous mode operation (IOUT > ILIM/2). For details of maximum output current in discontinuous mode operation, see Linear Technology's Application Note AN44. Finally, for duty cycles greater than 50% (VOUT/VIN > 0.5), a minimum inductance is required to avoid subharmonic oscillations. This minimum inductance is: SW1:LMIN = ( VOUT + VF ) * 0.45 fSW 0.9 fSW
Another constraint on the output capacitor is that it must have greater energy storage than the inductor; if the stored energy in the inductor transfers to the output, the resulting voltage step should be small compared to the regulation voltage. For a 5% overshoot, this requirement indicates: I COUT > 10 * L * LIM VOUT
2
SW2, SW3:LMIN = ( VOUT + VF ) * with LMIN in H and fSW in MHz.
The low ESR and small size of ceramic capacitors make them the preferred type for LT3507 applications. Not all ceramic capacitors are the same, however. Many of the higher value capacitors use poor dielectrics with high temperature and voltage coefficients. In particular, Y5V and Z5U types lose a large fraction of their capacitance with applied voltage and at temperature extremes. Because loop stability and transient response depend on the value of COUT, this loss may be unacceptable. Use X7R and X5R types.
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LT3507 APPLICATIONS INFORMATION
Electrolytic capacitors are also an option. The ESRs of most aluminum electrolytic capacitors are too large to deliver low output ripple. Tantalum, as well as newer, lower-ESR organic electrolytic capacitors intended for power supply use are suitable. Chose a capacitor with a low enough ESR for the required output ripple. Because the volume of the capacitor determines its ESR, both the size and the value will be larger than a ceramic capacitor that would give similar ripple performance. One benefit is that the larger capacitance may give better transient response for large changes in load current. Table 2 lists several capacitor vendors.
Table 2. Low ESR Surface Mount Capacitors
VENDOR Taiyo-Yuden AVX Kemet TYPE Ceramic Ceramic Tantalum Tantalum Tantalum Organic Aluminum Organic Tantalum or Aluminum Organic Aluminum Organic Ceramic TPS T491,T494,T495 T520 A700 POSCAP SP CAP SERIES
Table 3. Schottky Diodes
PART NUMBER On Semiconductor MBRM120E MBRM140 Diodes Inc B120 B140 B220 B240 DFLS140L DFLS240L 20 40 20 40 40 40 1 1 2 2 1 2 550 550 500 500 500 500 20 40 1 1 530 550 595 VR (V) IAVE (A) VF AT 1A (mV) VF AT 2A (mV)
Boost Pin Considerations The capacitor and diode tied to the BOOST pin generate a voltage that is higher than the input voltage. In most cases, a small ceramic capacitor and fast switching diode (such as the CMDSH-3 or MMSD914LT1) will work well. The capacitor value is a function of the switching frequency, peak current, duty cycle and boost voltage; in general a value of (0.1F * 1MHz/fSW) works well. Figure 3 shows three ways to arrange the boost circuit. The BOOST pin must be more than 2.5V above the SW pin for full efficiency. For outputs of 3.3V and higher, the standard circuit (Figure 3a) is best. For outputs between 2.8V and 3.3V, use a small Schottky diode (such as the BAT54). For lower output voltages, the boost diode can be tied to the input (Figure 3b). The circuit in Figure 3a is more efficient because the BOOST pin current comes from a lower voltage source. Finally, as shown in Figure 3c, the anode of the boost diode can be tied to another source that is at least 3V. For example, if you are generating 3.3V and 1.8V and the 3.3V is on whenever the 1.8V is on, the 1.8V boost diode can be connected to the 3.3V output. In this case, the 3.3V output cannot be set to track the 1.8V output (see Output Voltage Tracking). In any case, be sure that the maximum voltage at the BOOST pin is less than 55V and the voltage difference between the BOOST and SW pins is less than 25V. The minimum operating voltage of an LT3507 application is limited by the internal undervoltage lockout (4V for Channel 1, 3V for Channels 2 and 3) and by the
3507f
Sanyo Panasonic TDK
Diode Selection The catch diode (D1 from Figure 2) conducts current only during switch off time. Average forward current in normal operation can be calculated from: ID(AVG) = IOUT ( VIN - VOUT ) VIN
The only reason to consider a diode with a larger current rating than necessary for nominal operation is for the worst-case condition of shorted output. The diode current will then increase to the typical peak switch current. Peak reverse voltage is equal to the regulator input voltage. Use a diode with a reverse voltage rating greater than the input voltage. The programmable OVLO can protect the diode from excessive reverse voltage by shutting down the regulator if the input voltage exceeds the maximum rating of the diode. Table 3 lists several Schottky diodes and their manufacturers.
13
LT3507 APPLICATIONS INFORMATION
D2 D2 BOOST LT3507 VIN VIN GND VBOOST - VSW VOUT MAX VBOOST VIN + VOUT SW VOUT VIN VIN GND VBOOST - VSW VIN MAX VBOOST 2VIN D2 VINB > 3V BOOST LT3507 VIN VIN GND VBOOST - VSW VINB MAX VBOOST VINB + VIN MINIMUM VALUE FOR VINB = 3V SW VOUT C3 C3 BOOST LT3507 SW VOUT C3
(3a)
(3b)
3507 F03
(3c)
Figure 3. Generating the Boost Voltage
maximum duty cycle. The boost circuit also limits the minimum input voltage for proper start-up. If the input voltage ramps slowly, or the LT3507 turns on when the output is already in regulation, the boost capacitor may not be fully charged. Because the boost capacitor charges with the energy stored in the inductor, the circuit will rely on some minimum load current to get the boost circuit running properly. This minimum load will depend on input and output voltages, and on the arrangement of the boost circuit. The minimum load current generally goes to zero once the circuit has started. Figure 4 shows a plot of minimum load to start and to run as a function of input voltage. Even without an output load current, in
8.0 7.5 7.0 INPUT VOLTAGE (V) TO START 6.5 6.0 5.5 5.0 4.5 4.0 0.001 0.010 0.100 LOAD CURRENT (A) 1.000
3507 F04a
many cases the discharged output capacitor will present a load to the switcher that will allow it to start. The boost current is generally small but can become significant at high duty cycles. The required boost current is: IBOOST = VOUT VIN IOUT 40
Converter with Backup Output Regulator There is another situation to consider in systems where the output will be held high when the input to the LT3507 is absent. If the VIN and one of the RUN pins are allowed
5.5 5.0 INPUT VOLTAGE (V) 4.5 TO START 4.0 TO RUN 3.5 3.0 2.5 0.001 TA = 25C
TA = 25C
TO RUN
0.010 0.100 LOAD CURRENT (A)
1.000
3507 F04b
Figure 4. The Minimum Input Voltage Depends on Output Voltage, Load Current and Boost Circuit
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LT3507 APPLICATIONS INFORMATION
to float, then the LT3507's internal circuitry will pull its quiescent current through its SW pin. This is acceptable if the system can tolerate a few mA of load in this state. With all three RUN pins grounded, the LT3507 enters shutdown mode and the SW pin current drops to <50A. However, if the VIN pin is grounded while the output is held high, then parasitic diodes inside the LT3507 can pull large currents from the output through the SW pin and the VIN pin. A Schottky diode in series with the input to the LT3507, as shown in Figure 5, will protect the LT3507 and the system from a shorted or reversed input.
PARASITIC DIODE D4 VIN
and is largest when VIN = 2VOUT (50% duty cycle). As the second, lower power channel draws input current, the input capacitor's RMS current actually decreases as the out-of-phase current cancels the current drawn by the higher power channel. Considering that the maximum load current from a single phase (if SW2 and SW3 are both at maximum current) is ~3A, RMS ripple current will always be less than 1.5A. The high frequency of the LT3507 reduces the energy storage requirements of the input capacitor, so that the capacitance required is often less than 10F The combi. nation of small size and low impedance (low equivalent series resistance or ESR) of ceramic capacitors makes them the preferred choice. The low ESR results in very low voltage ripple. Ceramic capacitors can handle larger magnitudes of ripple current than other capacitor types of the same value. Use X5R and X7R types. An alternative to a high value ceramic capacitor is a lower value along with a larger electrolytic capacitor, for example a 1F ceramic capacitor in parallel with a low ESR tantalum capacitor. For the electrolytic capacitor, a value larger than 10F will be required to meet the ESR and ripple current requirements. Because the input capacitor is likely to see high surge currents when the input source is applied, tantalum capacitors should be surge rated. The manufacturer may also recommend operation below the rated voltage of the capacitor. Be sure to place the 1F ceramic as close as possible to the VIN and GND pins on the IC for optimal noise immunity. A final caution is in order regarding the use of ceramic capacitors at the input. A ceramic input capacitor can combine with stray inductance to form a resonant tank circuit. If power is applied quickly (for example by plugging the circuit into a live power source), this tank can ring, doubling the input voltage and damaging the LT3507. The solution is to either clamp the input voltage or dampen the tank circuit by adding a lossy capacitor in parallel with the ceramic capacitor. For details, see Application Note 88.
VIN
SW
VOUT
LT3507
3507 F05
Figure 5. Diode D4 Prevents a Shorted Input from Discharging a Backup Battery Tied to the Output
Input Capacitor Selection Bypass the input of the LT3507 circuit with a 10F or higher ceramic capacitor of X7R or X5R type. A lower value or a less expensive Y5V type will work if there is additional bypassing provided by bulk electrolytic capacitors, or if the input source impedance is low. The following paragraphs describe the input capacitor considerations in more detail. Step-down regulators draw current from the input supply in pulses with very fast rise and fall times. The input capacitor is required to reduce the resulting voltage ripple at the LT3507 input and to force this switching current into a tight local loop, minimizing EMI. The input capacitor must have low impedance at the switching frequency to do this effectively and it must have an adequate ripple current rating. With three switchers operating at the same frequency but with different phases and duty cycles, calculating the input capacitor RMS current is not simple; however, a conservative value is the RMS input current for the phase delivering the most power (VOUT * IOUT): IIN(RMS) =IOUT * VOUT ( VIN - VOUT ) VIN < IOUT 2
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LT3507 APPLICATIONS INFORMATION
Frequency Compensation The LT3507 uses current mode control to regulate the output. This simplifies loop compensation. In particular, the LT3507 does not depend on the ESR of the output capacitor for stability so you are free to use ceramic capacitors to achieve low output ripple and small circuit size. The components tied to the VC pin provide frequency compensation. Generally, a capacitor and a resistor in series to ground determine loop gain. In addition, there is a lower value capacitor in parallel. This capacitor filters noise at the switching frequency and is not part of the loop compensation. Loop compensation determines the stability and transient performance. Designing the compensation network is a bit complicated and the best values depend on the application and the type of output capacitor. A practical approach is to start with one of the circuits in this data sheet that is similar to your application and tune the compensation network to optimize the performance. Check stability across all operating conditions, including load current, input voltage and temperature. The LT1375 data sheet contains a more thorough discussion of loop compensation and describes how to test the stability using a transient load. Application Note 76 is an excellent source as well. Figure 6 shows an equivalent circuit for the LT3507 control loop. The error amp is a transconductance amplifier with finite output impedance. The power section, consisting of the modulator, power switch and inductor is modeled as a transconductance amplifier generating an output current proportional to the voltage at the VC pin. The gain of the power stage (gmp) is 5S for Channel 1 and 3.6S for Channels 2 and 3. Note that the output capacitor integrates this current and that the capacitor on the VC pin (CC) integrates the error amplifier output current, resulting in two poles in the loop. In most cases, a zero is required and comes either from the output capacitor ESR or from a resistor in series with CC. This model works well as long as the inductor current ripple is not too low (IRIPPLE > 5% IOUT) and the loop crossover frequency is less than fSW/5. A phase lead capacitor (CPL) across the feedback divider may improve the transient response.
CURRENT MODE POWER STAGE gmp ERROR AMPLIFIER FB VFB 800mV ESR LT3507 VSW R1 CPL OUTPUT
330S 500k GND VC R2 CF
RC CC
Figure 6. Loop Response Model
SHUTDOWN The RUN pins are used to place the individual switching regulators and the internal bias circuits in shutdown mode. When all three RUN pins are pulled low, the LT3507 is in shutdown mode and draws less than 1A from the input supply. When any RUN pin is pulled high (>1.5V) the internal reference, LDO and selected channel are all turned on. The RUN pins draw a small amount of current to power the reference. The current is less than 3A at 1.8V, so the RUN pin can be driven directly from 1.8V logic. The RUN pins are rated up to 36V and can be connected directly to the input voltage. A RUN pin cannot be pulled up by logic powered by its own output, i.e., RUN1 can't be pulled up by logic powered by OUT1. POWER GOOD INDICATORS The PGOOD pin is the open-collector output of an internal comparator. PGOOD remains low until the FB pin is within 10% of the final regulation voltage. Tie the PGOOD to any supply with a pull-up resistor that will supply less than 200A. Note that this pin will be open when the LT3507 is in shutdown mode (all three RUN pins at ground) regardless of the voltage at the FB pin. PGOOD is valid when the LT3507 is enabled (any RUN pin is high) and VIN is greater than ~3.5V.
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- +
+
C1 POLYMER OR TANTALUM
C1
CERAMIC
3507 F06
LT3507 APPLICATIONS INFORMATION
LT3507 RUN1 RUN2 RUN3 RUN1 RUN2 RUN3 RUN LT3507 RUN1 RUN2 RUN3 TRK/SS1 TRK/SS2 TRK/SS3 C 2C 4C LT3507 RUN RUN1 VINSW PG1 RUN2
(7a)
LT3507 RUN RUN1 RUN2 RUN3 TRK/SS1 PG1 TRK/SS2 PG2 TRK/SS3 VIN
(7b)
PG2 RUN3
(7c)
LT3507 RUN2 PG1
3507 F07
(7d)
(7e) Doesn't Work!
Figure 7. Output Sequencing
OUTPUT SEQUENCING The LT3507 outputs can be sequenced in several ways. The circuits in Figure 7 show some examples of these. In each case channel 1 starts first, followed by channel 2, then channel 3. The sequence shown is not a requirement; the LT3507 can sequence the channels in any order. Note that these circuits sequence the outputs during start-up. When shut down the three channels turn off simultaneously. The most obvious method is to bring the RUN pins up individually in the sequence desired (Figure 7a). This is the ideal solution if full independent control of all three channels is needed. This is also a simple solution, but it does require three logic inputs. Another possibility is to use the soft-start feature to slow the start-up of specific channels (Figure 7b). All three RUN pins are tied together and the difference in soft-start capacitance will determine the start-up sequence. The larger capacitor on channel 2 slows its start-up with respect to channel 1, and channel 3 is even slower. The capacitor on the delayed channel should be at least twice the value of the capacitor on the faster channel. A larger ratio may be required, depending on the output capacitance and load on each channel. Make sure to test the circuit in the system before deciding on final values for these capacitors. Also
remember that the delayed channels will start rising right away, just at a slower rate than the faster channels. The PG pins can be also used to sequence the three outputs. In Figure 7c, the PG pins drive the RUN pins directly. Channel 2 will be held off until channel 1 is in regulation and channel 3 is held off until channel 2 is in regulation. The resistors pull up to VINSW so that there is no current draw in shutdown. They should be sized to provide at least 1A into the RUN pin. The capacitors keep channels 2 and 3 off until the power good comparators are functioning (the power good comparators are disabled in shutdown). The FETs are necessary to insure the RUN2 and RUN3 pins are held low during shutdown. In Figure 7d, the PG pins pull down the TRK/SS pins of the delayed channels. This is a simple solution requiring no extra components. Channel 2 is held off by the PG1 output pulling TRK/SS2 down until channel 1 is at 90% of its final value. PG1 then goes high impedance and allows the channel 2 soft-start circuit to charge the soft-start capacitor bringing channel 2 up. Similarly, channel 3 is held off by PG2. The circuits in Figure 7a and 7b leave the power good indicators free. However, the circuits in Figures 7c and 7d have another advantage. As well as sequencing the outputs at start-up, they also disable the slaved channels
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LT3507 APPLICATIONS INFORMATION
VOUT1 OUTPUT VOLTAGE OUTPUT VOLTAGE VOUT1
VOUT2
VOUT2
3507 F08
TIME
TIME
(8a) Coincident Tracking
(8b) Ratiometric Tracking
Figure 8. Two Different Modes of Output Voltage Tracking
VOUT1 R5 TO TRK/SS2 PIN R6 R2 R1 TO VFB1 PIN TO VFB2 PIN R4 R3 VOUT2 SELECTING VALUES FOR R5 AND R6 R5 = R6 = COINCIDENT RATIOMETRIC R3 R1 R4 R1 VOUT1/1V - 1
Tracking Setup
R3 VOUT2 R1 VOUT1 = - 1, = -1 R4 0.8 R2 0.8
Figure 9. Setup for Coincident and Ratiometric Tracking
if the master channel falls out of regulation (due to a short circuit or a collapsing input voltage). Finally, be aware that the circuit in Figure 7e does not work, because the power good comparators are disabled in shutdown. OUTPUT VOLTAGE TRACKING The LT3507 allows the user to program how the output ramps up by means of the TRK/SS pins. Through these pins, any channel output can be set up to either coincidently or ratiometrically track any other channel output. This example will show the channel 2 output tracking the channel 1 output, as shown in Figure 8. The TRK/SS2 pin acts as a clamp on channel 2's reference voltage. VOUT2 is referenced to the TRK/SS2 voltage when the TRK/SS2 < 0.8V and to the internal precision reference when TRK/ SS2 > 0.8V. To implement the coincident tracking in Figure 8a, connect an extra resistive divider to the output of channel 1 and connect its midpoint to the TRK/SS2 pin (Figure 9). The ratio of this divider should be selected the same as that
of channel 2's feedback divider (R5 = R3 and R6 = R4). In this tracking mode, VOUT1 must be set higher than VOUT2. To implement the ratiometric tracking in Figure 8b, change the extra divider ratio to R5 = R1 and R6 = R2 + R. The extra resistance on R6 should be set so that the TRK/SS2 voltage is 1V when VOUT1 is at its final value. The need for this extra resistance is best understood with the help of the equivalent input circuit shown in Figure 10. At the input stage of the error amplifier, two common anode diodes are used to clamp the equivalent reference voltage and an additional diode is used to match the shifted common mode voltage. The top two current sources are of the same amplitude. In the coincident mode,
I 1A D1 TRK/SS 0.8V FB D3
3507 F10
I
+
D2 EA2
-
Figure 10. Equivalent Input Circuit of Error Amplifier
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LT3507 APPLICATIONS INFORMATION
the TRK/SS2 voltage is substantially higher than 0.8V at steady state and effectively turns off D1. D2 and D3 will therefore conduct the same current and offer tight matching between VFB2 and the internal precision 0.8V reference. In the ratiometric mode with R6 = R2, TRK/SS2 equals 0.8V at steady state. D1 will divert part of the bias current and make VFB2 slightly lower than 0.8V. Although this error is minimized by the exponential I-V characteristic of the diodes, it does impose a finite amount of output voltage deviation. Further, when channel 1's output experiences dynamic excursions (under load transient, for example), channel 2 will be affected as well. Setting R6 to a value that pushes the TRK/SS2 voltage to 1V at steady state will eliminate these problems while providing near ratiometric tracking. The example shows channel 2 tracking channel 1, however any channel may be set up to track any other channel. If a capacitor is tied from the TRK/SS pin to ground, then the internal pull-up current will generate a voltage ramp on this pin. This results in a ramp at the output, limiting the inductor current and therefore input current during start-up. A good value for the soft-start capacitor is COUT/10,000, where COUT is the value of the output capacitor. MULTIPLE INPUT SUPPLIES VIN1, VIN2 and VIN3 are independent and can be powered with different voltages provided VIN1 is present when VIN2 or VIN3 is present. Each supply must be bypassed as close to the VIN pins as possible. For applications requiring large inductors due to high VIN to VOUT ratios, a 2-stage step-down approach may reduce inductor size by allowing an increase in frequency. A dual step-down application steps down the input voltage (VIN1) to the highest output voltage, then uses that voltage to power the other outputs (VIN2 and VIN3). VOUT1 must be able to provide enough current for its output plus the input current at VIN2 and VIN3 when VOUT2 and VOUT3 are at maximum load. The Typical Applications section shows a 36V to 15V, 1.8V and 1.2V 2-stage converter using this approach. For applications with multiple voltages, the LT3507 can accommodate input voltages as low as 3V on VIN2 and VIN3. This can be useful in applications regulating outputs from a PCI Express bus, where the 12V input is power limited and the 3.3V input has power available to drive other outputs. In this case, tie the 12V input to VIN1 and the 3.3V input to VIN2 and VIN3. LOW DROPOUT REGULATOR The low dropout regulator comprises an error amp, loop compensation and a base drive amp. It uses the same 0.8V reference as the switching regulators. It requires an external NPN pass transistor and 2.2F of output capacitance for stability. The dropout characteristics will be determined by the pass transistor. The collector-emitter saturation characteristics will limit the dropout voltage. Table 4 lists some suitable NPN transistors with their saturation specifications. The base drive voltage has a maximum voltage of 5V. This will limit the maximum output of the regulator to 5V - VBESAT where VBESAT is the base-emitter saturation voltage of the pass transistor.
Table 4. NPN Pass Transistors and Saturation Characteristics
PART NUMBER On Semiconductor NSS30071 NSS30101 Fairchild KSC3265 0.4 500 20 0.25 0.2 0.85 0.85 500 1000 5 10 VCESAT VBESAT IC (mA) IB (mA)
The LDO is always on when any of the switcher channels is on. The LDO may be shut down if it is unused by pulling the FB4 pin up with a 30A current source. The FB4 pin will clamp at about 1.25V and the LDO will shut off reducing power consumption. This pull-up can be sourced from one of the LT3507 outputs provided that channel is always on when the other channels are on. The output stage of the LDO will drive the NPN base from the BIAS voltage if it is at least 0.8V above the LDO DRIVE voltage. FB Resistor Network The output voltage of the LDO regulator is programmed with a resistor divider (Refer to Block Diagram) between the
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LT3507 APPLICATIONS INFORMATION
emitter of the external NPN pass resistor and the feedback pin, FB4. Choose the resistors according to R1= R2 VOUT4 1 800mV The hysteresis voltages are: VOVHYST = 10A * R3 VUVHYST = 10A * R1 If the overvoltage lockout is not used, the OVLO pin must be tied to ground. If the undervoltage lockout is not used, the UVLO pin must be tied to VINSW.
VINSW 10A R1 R3 UVLO
The parallel combination of R1 and R2 should be 10k or less to avoid bias current errors. PROGRAMMABLE OVERVOLTAGE AND UNDERVOLTAGE LOCKOUT The LT3507 provides two input pins that allow user-programmable overvoltage and undervoltage lockout. Both the trip levels and hysteresis can be set by resistor values. VINSW provides a switched VIN1 to minimize power consumption in shutdown. VINSW is connected to VIN1 when the LT3507 is operating, with a saturation voltage of about 0.3V. It is high impedance when the LT3507 is in shutdown (all three RUN pins low). The programmable lockout is a pair of comparators with the trip level set at 1.2V. The OVLO comparator trips when the OVLO pin exceeds 1.2V while the UVLO comparator trips when the UVLO pin drops below 1.2V. These comparators shut down all four regulators until the input voltage recovers. The comparators also activate current sources that generate hysteresis to eliminate chatter. The UVLO comparator activates a 10A current sink on the UVLO pin. The OVLO comparator activates a 10A current source on the OVLO pin. These currents generate hysteresis voltage through the resistance of the divider string. Figure 11 shows a typical connection. The threshold voltages are: VOVTH = 0.3V + 1.2V * 1+ VUVTH = 0.3V + 1.2V * 1+ R3 R4 R1 R2
R2
OVLO R4 10A
Figure 11. Undervoltage and Overvoltage Lockout Circuit
PCB LAYOUT For proper operation and minimum EMI, care must be taken during printed circuit board (PCB) layout. Figure 12 shows the high current paths in the step-down regulator circuit. Note that in the step-down regulators large, switched currents flow in the power switch, the catch diode and the input capacitor. The loop formed by these components should be as small as possible. Place these components, along with the inductor and output capacitor, on the same side of the circuit board and connect them on that layer. Place a local, unbroken ground plane below these components and tie this ground plane to system ground at one location, ideally at the ground terminal of the output capacitor C2. Additionally, keep the SW and BOOST nodes as small as possible. Figure 13 shows an example of proper PCB layout.
20
+
1.2V
+
-
UVLO
-
OVLO
3507 F11
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LT3507 APPLICATIONS INFORMATION
VIN SW VIN SW
GND
GND
(12a)
VSW VIN IC1 SW L1
(12b)
C1
GND
D1
C2
(12c)
3507 F12
Figure 12. Subtracting the Current when the Switch is ON (12a) from the Current when the Switch is OFF (12b) Reveals the Path of the High Frequency Switching Current (12c) Keep this Loop Small. The Voltage on the SW and Boost Nodes will also be Switched; Keep These Nodes as Small as Possible. Finally, Make Sure the Circuit is Shielded with a Local Ground Plane
Figure 13. Power Path Components and Topside Layout
THERMAL CONSIDERATIONS The high output current capability of the LT3507 will require careful attention to power dissipation of all the components to insure a safe thermal design. The PCB must provide heat sinking to keep the LT3507 cool. The Exposed Pad on the bottom of the package must be soldered to a ground plane. This ground should be tied to other copper layers below with thermal vias; these layers will spread the heat
dissipated by the LT3507. Place additional vias near the catch diodes. Adding more copper to the top and bottom layers and tying this copper to the internal planes with vias can reduce thermal resistance further. With these steps, the thermal resistance from die (or junction) to ambient can be reduced to JA = 34C/W or less. With 100 LFPM airflow, this resistance can fall by another 25%. Further increases in airflow will lead to lower thermal resistance.
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LT3507 APPLICATIONS INFORMATION
The maximum allowed power dissipation by the LT3507 can be determined by: PDISS(MAX) = TJ(MAX) - TA JA where RSWi is the equivalent switch resistance (0.18 for channel 1 and 0.22 for channels 2 and 3) and f is the operating frequency. The boost loss in channel i is: VOUTi ( VBOOSTi ) IOUTi + 0.02A 50
where TJMAX is the maximum die temperature of 125C (150C for H grade). However, take care in determining TA since the catch diodes also dissipate power and must be located close to the LT3507. Another potential heat source is the LDO pass transistor. In a compact layout the pass transistor will be located close to the LT3507. The inductors will also dissipate some power due to their series resistance and they must be close to the LT3507. All of these heat sources will increase the effective ambient temperature seen by the LT3507. A thorough analysis of eight heat sources in a small PCB area is beyond the scope of this data sheet, however a number of thermal analysis programs are available to calculate the temperature rise in each component (such as PCAnalyze from K&K Associates or BETAsoft from Mentor). The power dissipation of each component will be needed to accurately calculate the thermal characteristics of the system. The contributors to power dissipation inside the LT3507 are switch DC loss, switch AC loss, boost current, quiescent current and LDO drive current. The total dissipation within the LT3507 can be expressed as: PDISS = (PSWDCi + PSWACi + PBSTi ) + PQ + PLDO
i=1 3
PBSTi =
VINi
The quiescent loss is: PQ = VIN1(IQ(VIN1)) + VBIAS(IQ(BIAS)) If the BIAS pin does not have a voltage of at least 3V applied, then VIN1 must replace VBIAS in the equation. Also, IQ(VIN1) can be reduced by 0.2mA (typ) if the LDO is shut off (see the LDO section). The LDO drive loss is: PLDO = (VBIAS VLDO(OUT) if VBIAS VLDO(OUT) + 1.5V or PLDO = (VIN1 VLDO(OUT) if VBIAS PASS
0.7V)
IOUT(LDO)
PASS
,
,
where PASS is the current gain of the external pass transistor. Next, the power in the external components must be taken into account. The diode power is given by: PDIODE = VF ( VIN - VOUT - VF )IOUT VIN
The switch DC and AC losses in channel i are: PSWDCi = RSWi (IOUTi ) VOUTi VINi
2
where VF is the forward drop of the diode at IOUT. The inductor power is: PIND = (IOUT)2 ESRIND where ESRIND is the inductor equivalent series resistance.
PSWACi = 17ns (IOUTi ) ( VINi ) ( f )
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22
LT3507 APPLICATIONS INFORMATION
The LDO pass transistor power is: PNPN = IOUTLDO(VC - VOUTLDO) where VC is the collector voltage on the NPN pass transistor. Example: An LT3507 design requirements are: VIN = 8V, f= 500kHz V1 = 2.5V at I1 = 1.6A V2 = 3.3V at I2 = 0.8A (used for boost, bias and V4) V3 = 1.2V at I3 = 1A V4 = 3V at I4 = 0.2A (from 3.3V output) TA = 50C, TJMAX = 125C JA = 34C/W Schottky VF = 0.45V and Inductor ESR = 0.05 PDISS(MAX) = PSWDC1 = 125C - 50C = 2.2W 34C/W The total dissipation on the LT3507 is the sum of all these and is equal to 0.73W. Note that this is less than half of PDISS(MAX). Next, the power dissipation of the external components are: PDIODE1 = 0.45V ( 8V - 2.5V - 0.45) 1.6A = 0.46W 8V
2
PIND1 = (1.6A ) 0.05 = 0.13W Similarly, PDIODE2 = 0.24W, PIND2 = 0.05W, PDIODE3 = 0.36W and PIND3 = 0.05W. And finally: PNPN = 0.2A(3.3V - 3V) = 0.06W Thus the total power dissipated by the LT3507 and external components is 2.08W. The thermal analysis will use these power dissipations to calculate the internal component temperatures. Make sure that none of the components exceed their rated temperature limits. RELATED LINEAR TECHNOLOGY PUBLICATIONS Application Notes 19, 35, 44, 76 and 88 contain more detailed descriptions and design information for buck regulators and other switching regulators. The LT1375 data sheet has a more extensive discussion of output ripple, loop compensation, and stability testing. Design Note 318 shows how to generate a dual polarity output supply using a buck regulator.
= 0.14W 8V PSWAC1 = 17ns (1.6A ) ( 8V ) ( 500k ) = 0.11W 2.5V ( 3.3V ) 1.6A + 0.02A 50 = 0.06W 8V
0.18
(1.6A )
2
2.5V
PBST1 =
Similarly, PSWDC2 = 0.09W, PSWAC2 = 0.07W, PBST2 = 0.06W, PSWDC3 = 0.03W, PSWAC3 = 0.07W and PBST2 = 0.03W. Remember, the total current from channel 2 is I2 + I4 since the LDO pass transistor draws from V2. Ignore bias and boost currents. PQ = 8V ( 3.5mA ) + 3.3V ( 7.5mA ) = 0.05W PLDO = 8V 0.2A = 0.02W 100
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23
LT3507 TYPICAL APPLICATIONS
3.3V, 5V and 12V from a 24V Input with Ratiometric Tracking
VIN 21V TO 27V BAT54 VOUT1 3.3V 2A L1 3.3H 41.2k 22F 13.3k D1 16.2k 1000pF 100k 10F 50V 0.1F SW1 FB1 100k VC1 1.5nF TRK/SS1 41.2k BAT54 VOUT2 5V 1.2A L2 6.8H 61.9k 22F 11.8k D2 24.3k BIAS RUN1 RUN2 RUN3 RT/SYNC 54.9k fSW = 800kHz GND
3507 TA02
4.53k OVLO = 29V 4.32k UVLO = 16V
49.9k VIN1 BOOST1 VIN2 VIN3 VINSW UVLO OVLO
VOUT1
100k
100k PGOOD1 PGOOD2 PGOOD3 VOUT1
PGOOD1 PGOOD2 PGOOD3 BOOST3 BAT54 0.1F LT3507 L3 10H SW3 FB3 470pF VC3 26.7k 10.7k D3 150k
18.2k
TRK/SS2 TRK/SS3 BOOST2 0.1F SW2 FB2 470nF VC2
VOUT3 12V 1A 10F
VOUT1 NC 68.1k D1: ON SEMI MBRS230LT3 D2, D3: ON SEMI MBRA130LT3 L1: COILCRAFT DO1813H-332ML L1: COILCRAFT DO1813H-682ML L1: COILCRAFT DO1813H-103ML
SHDN
DRIVE FB4 TRK/SS4
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24
LT3507 TYPICAL APPLICATIONS
5V, 3.3V, 2.5V and 1.8V with Coincident Tracking
VIN 6V TO 36V 49.9k 22F VIN1 VOUT2 VOUT1 1.8V 2.4A BOOST1 4.7H 18.7k 100F 15k 18.7k 15k TRK/SS1 18.7k VOUT3 5V 1.5A 35.7k TRK/SS2 11.5k 22F 10.2k D2 VOUT2 15H 53.6k 680pF VC3 24.3k 0.01F TRK/SS3 RUN1 RUN2 RUN3 RT/SYNC GND
3507 TA03
18.2k
VIN2
VIN3 VINSW UVLO OVLO VOUT1
0.22F SW1 680pF FB1
D1
100k VC1 PGOOD1 PGOOD2 PGOOD3 LT3507 BOOST2 0.22F BOOST3 SW2 FB2 SW3 FB3 VC2 16.2k 1000pF D3
100k
100k PGOOD1 PGOOD2 PGOOD3
10H 35.7k
0.22F
VOUT2 3.3V 1.3A 22F
11.5k
TRK/SS2 BIAS DRIVE FB4 TRK/SS4 2.2nF
TRK/SS2
Q1 VOUT4 2.5V 0.2A
L1: WURTH WE-PD 744 778 9004 L2: WURTH WE-PD 744 778 9115 L3: WURTH WE-PD 744 778 910 105k D1, D2, D3: DIODES, INC. B240A Q1: ON SEMICONDUCTOR NSS30101LT1G
SHDN
24.3k
22F
fSW = 450kHz
11.5k
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25
LT3507 TYPICAL APPLICATIONS
15V, 1.8V and 1.2V 2-Stage Step Down
VIN 21V TO 36V
10F 49.9k 22F VIN1 BOOST1 VIN2 VIN3 VINSW UVLO OVLO 3.4k UVLO = 19V
VOUT1 15V 0.4A
L1 10H 187k D1 10.5k 68.1k
0.1F SW1 220pF FB1 VC1 0.01F TRK/SS1 BIAS LT3507 TRK/SS2 TRK/SS3 PGOOD1 PGOOD2 PGOOD3 BOOST 2 0.1F SW2 FB2 1000pF VC2 13.3k 18.2k D2 L2 3.3H 22.6k 33F VOUT2 100k PGOOD VBST VOUT2 1.8V 1.5A
Q1 VBST 3V 2.2F 31.6k
DRIVE FB4 TRK/SS4 11.5k 270pF
BOOST3 RUN1 RUN2 RUN3 RT/SYNC 54.9k fSW = 800kHz GND 0.1F SW3 FB3 1000pF D1: DIODES, INC. B140A D2, D3: DIODES, INC. B240A L1: TDK LTF5022T-100M1R4 L2: TDK VLCF5020T-3R3N2R0-1 L3: TDK VLCF5020T-2R2N1R7 Q1: DIODES INC. BC817-16 VC3 12.7k 30.1k D3 L3 2.2H 15.0k
VBST VOUT3 1.2V 1.5A 47F
SHDN
3507 TA04
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26
LT3507 PACKAGE DESCRIPTION
UHF Package 38-Lead Plastic QFN (5mm x 7mm)
(Reference LTC DWG # 05-08-1701)
0.70 0.05
5.50 0.05 (2 SIDES) 4.10 0.05 (2 SIDES) 3.15 0.05 (2 SIDES)
PACKAGE OUTLINE 0.25 0.05 0.50 BSC 5.15 0.05 (2 SIDES) 6.10 0.05 (2 SIDES) 7.50 0.05 (2 SIDES) RECOMMENDED SOLDER PAD LAYOUT 5.00 0.10 (2 SIDES) 0.75 0.05 0.00 - 0.05 3.15 0.10 (2 SIDES) PIN 1 NOTCH R = 0.30 TYP OR 0.35 x 45 CHAMFER 37 38 0.40 0.10 1 2
PIN 1 TOP MARK (SEE NOTE 6)
7.00 0.10 (2 SIDES)
5.15 0.10 (2 SIDES)
0.40 0.10 0.200 REF 0.25 0.05 0.75 0.05 0.200 REF 0.00 - 0.05 0.50 BSC R = 0.115 TYP
(UH) QFN 0205
BOTTOM VIEW--EXPOSED PAD
NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE M0-220 VARIATION WHKD 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
3507f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LT3507 TYPICAL APPLICATIONS
12V to 5V, 3.3V, 1.8V and 1.6V with 1.5mm Maximum Height
VIN 8V TO 16V 49.9k 10F VIN1 BOOST1 VOUT1 1.8V 2A L1 2H 22.6k 33F 18.2k D1 13.3k 1000pF 0.1F SW1 FB1 VC1 1.5nF TRK/SS1 L2 4.5H 41.2k 10F 13.3k D2 7.32k 2000pF VC2 1.5nF TRK/SS2 RUN1 RUN2 RUN3 RT/SYNC 31.6k fSW = 1.25MHz GND TRK/SS3 BIAS DRIVE FB4 TRK/SS4 2.2nF VOUT2 VOUT1 Q1 VOUT4 1.6V 0.2A 22F 20.0k
3507 TA03
4.02k OVLO = 17V 11.3k UVLO = 7V
49.9k VIN2 VIN3 VINSW UVLO OVLO
VOUT2 VOUT1 100k 100k 100k PGOOD1 PGOOD2 PGOOD3 VOUT2 0.1F L3 4.5H 61.9k 1200pF D3 11.3k 11.8k 10F VOUT3 5V 1.4A
PGOOD1 PGOOD2 PGOOD3 BOOST3 SW3 LT3507 FB3 VC3 1.5nF
BOOST2 0.1F SW2 FB2
VOUT2 3.3V 1.5A
D1: DIODES, INC. DFLS220L D2, D3: DIODES, INC. DFLS120L L1: COOPER SD14-2R0-R L2, L3: COOPER SD14-4R5-R Q1: ON SEMI NSS30071MR6T1G
SHDN
20.0k
RELATED PARTS
PART NUMBER DESCRIPTION LT1939 LT1940 LT3480 LT3481 LT3493 LT3500 LT3501/10 LT3505 LT3506/A LT3508 LT3684 LT3685 25V, 2A, 2.5MHz High Efficiency DC/DC Converter and LDO Controller Dual 25V, 1.4A (IOUT), 1.1MHz, High Efficiency Step-Down DC/DC Converter 36V with Transient Protection to 60V, 2A (IOUT), 2.4MHz, High Efficiency Step-Down DC/DC Converter with Burst Mode Operation 34V with Transient Protection to 36V, 2A (IOUT), 2.8MHz, High Efficiency Step-Down DC/DC Converter with Burst Mode Operation 36V, 1.4A (IOUT), 750kHz High Efficiency Step-Down DC/DC Converter 36V, 40Vmax, 2A, 2.5MHz High Efficiency DC/DC Converter and LDO Controller 25V, Dual 3A/2A (IOUT), 1.5MHz High Efficiency Step-Down DC/DC Converter 36V with Transient Protection to 40V, 1.4A (IOUT), 3MHz, High Efficiency Step-Down DC/DC Converter 25V, Dual 1.6A (IOUT), 575kHz,/1.1MHz High Efficiency Step-Down DC/DC Converter 36V with Transient Protection to 40V, Dual 1.4A (IOUT), 3MHz, High Efficiency Step-Down DC/DC Converter 34V with Transient Protection to 36V, 2A (IOUT), 2.8MHz, High Efficiency Step-Down DC/DC Converter 36V with Transient Protection to 60V, 2A (IOUT), 2.4MHz, High Efficiency Step-Down DC/DC Converter COMMENTS VIN(MIN) = 3.6V, VIN(MAX) = 25V, VOUT(MIN) = 0.8V, IQ = 2.5mA, ISD < 10A, 3 x 3 DFN-10 Package VIN(MIN) = 3.3V, VIN(MAX) = 25V, VOUT(MIN) = 1.20V, IQ = 3.8mA, ISD < 30A, TSSOP16E Package VIN(MIN) = 3.6V, VIN(MAX) = 38V, VOUT(MIN) = 0.78V, IQ = 70A, ISD < 1A, 3 x 3 DFN-10, MSOP-10E Package VIN(MIN) = 3.6V, VIN(MAX) = 34V, VOUT(MIN) = 1.26V, IQ = 50A, ISD < 1A, 3 x 3 DFN-10, MSOP-10E Package VIN(MIN) = 3.6V, VIN(MAX) = 36V, VOUT(MIN) = 0.8V, IQ = 1.9mA, ISD < 1A, 2 x 3 DFN-6 Package VIN(MIN) = 3.6V, VIN(MAX) = 36V, VOUT(MIN) = 0.8V, IQ = 2.5mA, ISD < 10A, 3 x 3 DFN-10 Package VIN(MIN) = 3.3V, VIN(MAX) = 25V, VOUT(MIN) = 0.8V, IQ = 3.7mA, ISD = 10A, TSSOP-20E Package VIN(MIN) = 3.6V, VIN(MAX) = 34V, VOUT(MIN) = 0.78V, IQ = 2mA, ISD = 2A, 3 x 3 DFN-8, MSOP-8E Package VIN(MIN) = 3.6V, VIN(MAX) = 25V, VOUT(MIN) = 0.8V, IQ = 3.8mA, ISD = 30A, TSSOP-16E, 5 x 4 DFN-16 Package VIN(MIN) = 3.7V, VIN(MAX) = 37V, VOUT(MIN) = 0.8V, IQ = 4.6mA, ISD = 1A, 4 x 4 QFN-24, TSSOP-16E Package VIN(MIN) = 3.6V, VIN(MAX) = 34V, VOUT(MIN) = 1.26V, IQ = 850A, ISD < 1A, 3 x 3 DFN-10, MSOP-10E Package VIN(MIN) = 3.6V, VIN(MAX) = 38V, VOUT(MIN) = 0.78V, IQ = 70A, ISD < 1A, 3 x 3 DFN-10, MSOP-10E Package
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ThinSOT is a trademark of Linear Technology Corporation. Burst Mode is a registered trademark of Linear Technology Corporation.
28 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0408 * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2008

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